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commercial temperature range IDTCV119E clock generator for desktop pc platforms 1 january 2004 IDTCV119E commercial temperature range clock generator for desktop pc platforms xtal osc amp sm bus controller watch dog timer control logic cpu clk output buffers 3v66/pci output buffers src clk output buffer 48mhz output buffer x1 x2 sdata sclk v tt_pwrgd fs[1:0] s el 24_48# i ref i ref cpu[1:0] cpu_itp ref 1.0 pci[5:0], pcif[2:0] 3v66[3:1] src 48mhz[1:0] pll3 ssc pll4 pll1 ssc easyn programming pll2 ssc easyn programming reset# the idt logo is a registered trademark of integrated device technology, inc. ? 2004 integrated device technology, inc. dsc-6551/6 features: ? 4 pll architecture ? linear frequency programming ? independent frequency programming and ssc control ? band-gap circuit for differential output ? high power-noise rejection ratio ? 66mhz to 533mhz cpu frequency ? vco frequency up to 1.1g ? support index block read/write, single cycle index block read ? programmable ref, 3v66, pci, 48mhz i/o drive strength ? programmable 3v66 and pci skew ? available in ssop package functional block diagram description: IDTCV119E is a 48 pin clock generation device for desktop pc platforms. this chip incorporates four plls to allow independent generation of cpu, agp/ pci, src, and 48mhz clocks. the dedicated pll for serial ata clock provides high accuracy frequency. this device also implements band-gap referenced i ref to reduce the impact of v dd variation on differential outputs, which can provide more robust system performance. static pll frequency divide error can be as low as 36 ppm, providing high accuracy output clock. each cpu, agp/pci, src clock has its own spread spectrum selection. key specification: ? cpu/src clk cycle to cycle jitter < 125ps ? sata clk cycle to cycle jitter < 125ps ? pci clk cycle to cycle jitter < 250ps ? static pll frequency divide error as low as 36 ppm output table cpu (pair) 3v66 3v66/vch pci pcif ref 48mhz 24 - 48mhz src (pair) reset# 3316322 0 11
commercial temperature range 2 IDTCV119E clock generator for desktop pc platforms pin configuration symbol description min max unit v dda 3.3v core supply voltage 4.6 v v ddin 3.3v logic input supply voltage gnd - 0.5 4.6 v t stg storage temperature ?65 +150 c t ambient ambient operating temperature 0 +70 c t case case temperature +115 c esd prot input esd protection 2000 v human body model absolute maximum ratings (1) note: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. ssop top view 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 v dda v ss iref v ss cput1 cpuc1 v dd_ cpu cput0 cpuc0 v ss srct srcc v dd_ src *v tt _p wrgd# *sdata *sclk reset# 3v66_1 v ss v dd_ 3v66 3v66_2 3v66_3/vch 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 *fs1/ref0 *fs0/ref1 v dd _ref x1 x2 v ss pcif0 pcif1 pcif2 v ss v ss pci0 pci1 pci2 pci3 v dd_ pci v dd_ pci pci4 pci5 *reset#/pd# **sel24/24_48mhz# 48mhz0 v ss v dd 48 cput_itp cpuc_itp hw frequency selection fs1.0 cpu agp pci n resolution 00 100 66.66 33.3 0.223721591 01 200 66.66 33.3 0.447443181 10 133.33 66.66 33.3 0.298295454 11 166.67 66.66 33.3 0.397727272 * = ~ 130k ? internal pull-up. ** = ~ 130k ? internal pull-down.
commercial temperature range IDTCV119E clock generator for desktop pc platforms 3 spread spectrum magnitude control (smc) smc[2:0] 000 off 001 - 0.25 010 - 0.5 011 - 0.75 100 - 1 101 0.125 110 0.25 111 0.375 afs[2:0] agp pci corresponding n 000 66.67 33.33 298 001 68.68 34.34 307 010 70.7 35.35 316 011 72.71 36.35 325 100 74.5 37.25 333 101 76.51 38.26 342 110 78.53 39.26 351 111 80.54 40.27 360 3v66-pci/f skew skew[2:0] 000 normal, 3v66 leads pci 2.5ns 001 move forward 200ps 010 move forward 400ps 011 move forward 600ps 100 move backward 200ps 101 move backward 400ps 110 move backward 600ps 111 move backward 800ps wdbs[2:0] or wdbs[2:0] or wdbs[2:0] or wdbs[2:0] or wdbs[2:0] or wdbs[2:0] or wdbs[2:0] or wdbs[2:0] or cfs[3:0] bs[2:0] = 000 bs[2:0] = 001 bs = 010 bs[2:0] = 011 bs[2:0] = 100 bs[2:0] = 101 bs[2:0] = 110 bs[2:0] = 111 000 100 200.01 133.34 166.65 200.01 400.01 266.66 333.3 001 100.9 201.8 135.13 167.84 66.67 401.8 267.57 334.89 010 102.91 204.93 138.11 169.83 011 104.93 209.85 139.9 173.01 100 110.07 215.22 141.99 175 101 114.99 220.14 144.97 178.18 110 119.91 225.06 147.95 180.17 111 125.06 229.99 150.05 184.94 n resolution 0.223721591 0.447443181 0.298295454 0.397727272 0.447443181 0.894886363 0.894886363 0.795454544 corresponding n 447 447 447 419 447 447 298 419 sw frequency selection bs[2:0] and wbs[2:0] are band selects. whenever there is a band switch, the user has to issue a wd soft alarm (see byte 32 and byte 33). in cpu n/m programming, cpu frequency = n * resolution. agp/pci frequency selection in agp/pci n/m programming, agp frequency = n * 0.223721591 agp/pci strength str[1:0] 0, 0 2h (1) 0, 1 1l (2) 1, 0 1h (2) 1, 1 2l (1) ref strength ref str[1:0] 0, 0 2l (1) 0, 1 1h (2) 1, 0 2h (1) 1, 1 1l (2) notes: 1. recommended for multiple load. 2. recommended for single load. notes: 1. recommended for multiple load. 2. recommended for single load.
commercial temperature range 4 IDTCV119E clock generator for desktop pc platforms pin description pin number name type description 1 fs1/ref0 i/o frequency select latch input 3.3v input high/low voltage/ 14.318mhz reference clock output (1) 2 fs0/ref1 i/o frequency select latch input 2.5v input high/low voltage/ 14.318mhz reference clock output (1) 3v dd _ref pwr 3.3v 4 x1 i n xtal input 5 x2 out xtal output 6v ss gnd gnd 7 pcif0 i/o frequency select latch input 3.3v input high/low voltage/ pci free running clock (2) 8 pcif1 out pci free running clock 9 pcif2 out pci free running clock 10 v dd _pci pwr 3.3v 11 v ss gnd gnd 12 pci0 out pci clock 13 pci1 out pci clock 14 pci2 out pci clock 15 pci3 out pci clock 16 v dd _pci pwr 3.3v 17 v ss gnd gnd 18 pci4 out pci clock 19 pci5 out pci clock 20 reset#/pd# out reset output signal from watchdog circuit, active low/ power down control input. mode selectable through sm bus, power on is reset# mode. (1) byte 34 bit 5. 21 sel24/24_48mhz# out 24/48mhz clock output, low 48mhz (2) 22 48mhz0 out 48mhz clock output. phase is 180 different with 24_48, 48mhz1, and vch. output drive stength can be doubled through sm programming. 23 v ss gnd gnd 24 v dd 48 pwr 3.3v 25 3v66_3/vch out 66mhz or 48mhz clock output. selectable by sm bus. power on is 66mhz. 26 3v66_2 out 66mhz clock output 27 v dd _3v66 pwr 3.3v 28 v ss gnd gnd 29 3v66_1 out 66mhz clock output 30 reset# out reset# 31 sclk in smbus clock (1) 32 sdata i/o smbus data (1) 33 v tt _p wrgd # i n used for power on latch, active low (1) 34 v dd _src pwr 3.3v 35 srcc out sata 0.7v current mode differential clock output 36 srct out sata 0.7v current mode differential clock output 37 v ss gnd gnd 38 cpuc0 out hosts 0.7v current mode differential clock output 39 cput0 out hosts 0.7v current mode differential clock output 40 v dd _cpu pwr 3.3v notes: 1. ~ 130k ? internal pull-up. 2. ~ 130k ? internal pull-down.
commercial temperature range IDTCV119E clock generator for desktop pc platforms 5 pin description (cont.) pin number name type description 41 cpuc1 out hosts 0.7v current mode differential clock output 42 cput1 out hosts 0.7v current mode differential clock output 43 v ss gnd gnd 44 cpuc_itp out hosts 0.7v current mode differential clock output 45 cput_itp out hosts 0.7v current mode differential clock output 46 iref out reference current for differential output 47 v ss gnd gnd 48 v dda pwr 3.3v
commercial temperature range 6 IDTCV119E clock generator for desktop pc platforms onecycle? index block read bit # of bits from description 1 1 master start 2-9 8 master d2h 10 1 slave acknowledge 11-18 8 master r egister offset byte (starting byte) 19 1 slave acknowledge 20-27 8 master 1xxxxxxx. bit[20] = 1, followed with byte count, which will be stored into smbus table byte 8. 28 1 slave acknowledge 29 1 master repeated start 30-37 8 master d3h 38 1 slave acknowledge 39-46 8 slave byte count, n, smbus table byte 8 value. power on default is 0fh[15]. 47 1 master acknowledge 48-55 8 slave offset data byte, specified by bit[11:18] 56 1 master acknowledge 57-64 8 slave offset + 1 data byte : slave offset + n-2 master acknowledge slave offset + n-1 not acknowledge stop byte read methods (chose one): ? use idt onecycle index block read, bit[20:27] = 10000001. notice that byte count register (byte 8) will be changed to 0ih. ? use index block write protocol to change byte count (byte 8) to 1. after that, use index block read. to change byte 8 value: ? use idt onecycle index block read, as above ? use index block write protocol to change byte 8 value. smbus protocol index block read protocol bit # of bits from description 1 1 master start 2-9 8 master d2h 10 1 slave acknowledge 11-18 8 master reg ister offset byte (starting byte) 19 1 slave acknowledge 20 1 master repeated start 21-28 8 master d3h 29 1 slave acknowledge 30-37 8 slave byte count, n, smbus table byte 8 value. power on default is 0fh[15]. 38 1 master acknowledge 39-46 8 slave offset data byte, specified by bit 11-18 47 1 master acknowledge 48-55 8 slave offset + 1 data byte : slave offset + n-2 master acknowledge slave offset + n-1 not acknowledge stop index block write protocol bit # of bits from description 1 1 master start 2-9 8 master d2h 10 1 slave acknowledge 11-18 8 master reg ister offset byte (starting byte) 19 1 slave acknowledge 20-27 8 master byte count n (0 is not a valid byte count) (1) 28 1 slave acknowledge 29-36 8 master first data byte 37 1 slave acknowledge 38-45 8 master second data byte 46 1 slave acknowledge : nth data byte stop note: 1. bit [21:27] = byte count. bit 20 = 1, bit [21:27] will be stored into smbus table, byte 8. smbus byte 8 is read byte count register, power on default is 0fh. bit 20 = 0, normal smbus operation. byte write methods: ? setting bit[11:18] = starting address, bit [20:27] = 01h.
commercial temperature range IDTCV119E clock generator for desktop pc platforms 7 byte 0: dummy byte byte 1 bit output(s) affected description/function 0 1 type power on 7 reserve 0 6 reserve 0 5 ss_en spread spectrum enable on off rw 1 4 reserve 0 3 srct, srcc output enable tristate enable rw 1 2 cput_itp, cpuc_itp output enable tristate enable rw 1 1 cput1, cpuc1 output enable tristate enable rw 1 0 cput0, cpuc0 output enable tristate enable rw 1 byte 2 bit output(s) affected description/function 0 1 type power on 7 srct srct powerdown drive mode driven in power down tristate in power down rw 0 6 reserve 0 5 cput1, 0 cput powerdown drive mode driven in power down tristate in power down rw 0 4 reserve 0 3 3v66_2 output enable tristate enable rw 1 2 reserve 1 1 reserve 1 0 reserve 1 byte 3 bit output(s) affected description/function 0 1 type power on recommended 7 reserve 0 6 reserve rw 1 0 5 pci5 output enable tristate enable rw 1 4 pci4 output enable tristate enable rw 1 3 pci3 output enable tristate enable rw 1 2 pci2 output enable tristate enable rw 1 1 pci1 output enable tristate enable rw 1 0 pci0 output enable tristate enable rw 1
commercial temperature range 8 IDTCV119E clock generator for desktop pc platforms byte 5 bit output(s) affected description/function 0 1 type power on 7 3v66_3/vch 3v66_3/ vch mode select 3v66 mode, 66mhz vch mode, 48mhz rw 0 6 reserve 0 5 reserve 0 4 3v66_3/vch output enable tristate enable rw 1 3 reserve 0 2 reserve 0 1 reserve 0 0 reserve 0 byte 7 bit output(s) affected description/function 0 1 type power on 7 rid3 x 6 rid2 x 5 rid1 x 4 rid0 x 3 vid3 0 2 vid2 1 1 vid1 0 0 vid0 1 byte 6: dummy byte byte 4 bit output(s) affected description/function 0 1 type power on recommended 7 48mhz0 drive strength 2 * drive normal rw 0 1 6 srcfs0 src frequency select 100mhz 200mhz rw 0 5 reserve rw 1 0 4 3v66_1 output enable tristate enable rw 1 3 10 2 pcif2 output enable tristate enable rw 1 1 pcif1 output enable tristate enable rw 1 0 pcif0 output enable tristate enable rw 1
commercial temperature range IDTCV119E clock generator for desktop pc platforms 9 byte 8 (read byte count register) bit output(s) affected description/function 0 1 type power on 7 reserve 0 6 bc6 see note 1 0 5 bc5 0 4 bc4 0 3 bc3 1 2 bc2 1 1 bc1 1 0 bc0 1 note: 1. can be written by index block write or onecycle block read. see smbus protocol tables. bytes 9-20: dummy bytes byte 21 bit output(s) affected description/function 0 1 type power on 7 pcifstr1 agp/pci strength table 1 6 pcifstr0 agp/pci strength table 1 5 reserve 1 4 reserve 1 3 reserve 1 2 reserve 1 1 3v66str1 agp/pci strength table 1 0 3v66str0 agp/pci strength table 1 byte 22 bit output(s) affected description/function 0 1 type power on recommended 7 refstr1 ref strength table 1 6 refstr0 ref strength table 0 5 pcistrc1 pci[7:5] strength control, agp/pci strength table 1 1 4 pcistrc0 pci[7:5] strength control, agp/pci strength table 1 0 3 pcistrb1 pci[4:2] strength control, agp/pci strength table 1 1 2 pcistrb0 pci[4:2] strength control, agp/pci strength table 1 0 1 pcistra1 pci[1:0] strength control, agp/pci strength table 1 1 0 pcistra0 pci[1:0] strength control, agp/pci strength table 1 0
commercial temperature range 10 IDTCV119E clock generator for desktop pc platforms byte 24 bit output(s) affected description/function 0 1 type power on 7 wdhrb wd hard alarm status read back r 6 wdsrb wd soft alarm status read back r 5 4 3 2 0 1 fsr1 hw fs1 read back r hw fs1 0 fsr0 hw fs0 read back r hw fs0 byte 25: cpu pll control bit output(s) affected description/function 0 1 type power on 7 cpu frequency band source select 0 = selected by hw latched fs[1:0], cfs[2:0] hw sw rw 0 1 = selected by bs[2:0], cfs[2:0] 6 bs2, band select 2 bs[2:0] cfs[2:0] select cpu frequency (1) rw 0 5 bs1, band select 1 bs[2:0] cfs[2:0] select cpu frequency (1) rw 0 4 bs0, band select 0 bs[2:0] cfs[2:0] select cpu frequency (1) rw 0 3 cfs2 bs[2:0] cfs[2:0] select cpu frequency (1) rw 0 2 cfs1 bs[2:0] cfs[2:0] select cpu frequency (1) rw 0 1 cfs0 bs[2:0] cfs[2:0] select cpu frequency (1) rw 0 0 cpu n programming enable cpu n programming enable disable enable rw 0 notes: 1. see sw frequency selection table. byte 23 bit output(s) affected description/function 0 1 type power on recommended 7 48mhz0 output enable tristate enable rw 1 6 24_48mhz output enable tristate enable rw 1 5 ref1 output enable tristate enable rw 1 4 ref0 output enable tristate enable rw 1 3 reserve 10 2 reserve output enable tristate enable rw 1 0 1 reserve output enable tristate enable rw 1 0 0 reserve 0
commercial temperature range IDTCV119E clock generator for desktop pc platforms 11 byte 26: cpu pll control bit output(s) affected description/function 0 1 type power on 7 wdbs2 at the event of wd hard alarm time out, rw 1 6 wdbs1 if byte 32 bit 7 = 1, cpu frequency is rw 0 5 wdbs0 selected by wdbs[2:0] wdcfs[2:0] (1) rw 0 4 csmc2 cpu smc2, smc table rw 0 3 csmc1 cpu smc1, smc table rw 1 2 csmc0 cpu smc0, smc table rw 0 1 cpn9 cpu pll n9 rw 0 0 cpn8 cpu pll n8 rw 1 note: 1. see sw frequency selection table. byte 27: cpu pll n programming in cpu n programming mode, cpu frequency = cpn[9:0] * band resolution. cpn0 has to be written for the cpn[9:0] to be loaded i nto pll n divider. see sw frequency selection table. bit output(s) affected description/function 0 1 type power on 7 cpn7 cpu pll n7 rw 0 6 cpn6 cpu pll n6 rw 0 5 cpn5 cpu pll n5 rw 1 4 cpn4 cpu pll n4 rw 0 3 cpn3 cpu pll n3 rw 1 2 cpn2 cpu pll n2 rw 0 1 cpn1 cpu pll n1 rw 1 0 cpn0 cpu pll n0 rw 0 byte 28: agp/pci pll control bit output(s) affected description/function 0 1 type power on 7 afs2 see agp/pci frequency selection table rw 0 6 afs1 see agp/pci frequency selection table rw 0 5 afs0 see agp/pci frequency selection table rw 0 4 wdafs2 agp/pci wd hard alarm time out frequency selection rw 0 3 wdafs1 agp/pci wd hard alarm time out frequency selection rw 0 2 wdafso agp/pci wd hard alarm time out frequency selection rw 0 1 apn9 agp/pci pll n9 rw 0 0 apn8 agp/pci pll n8 rw 1
commercial temperature range 12 IDTCV119E clock generator for desktop pc platforms byte 29: agp/pci n programming in agp/pci n programming mode, agp/pci frequency = apn[9:0] * 0.223721591. apn0 has to be written for the apn[9:0] to be load ed into pll n divider. bit output(s) affected description/function 0 1 type power on 7 apn7 agp/pci pll n7 rw 0 6 apn6 agp/pci pll n6 rw 0 5 apn5 agp/pci pll n5 rw 1 4 apn4 agp/pci pll n4 rw 0 3 apn3 agp/pci pll n3 rw 1 2 apn2 agp/pci pll n2 rw 0 1 apn1 agp/pci pll n1 rw 1 0 apn0 agp/pci pll n0 rw 0 byte 30: agp/pci src control bit output(s) affected description/function 0 1 type power on 7 agp/pci n programming mode enable agp/pci n programming enable disable enable rw 0 6 agp/pci frequency source select 0 = fixed 66/33mhz 66/33mhz rw 0 1 = selected by afs[2:0] (1) 5 agp smc 2 agp/pci ssc magnitude control (2) rw 0 4 agp smc 1 agp/pci ssc magnitude control (2) rw 1 3 agp smc 0 agp/pci ssc magnitude control (2) rw 0 2 3v66-pci/f skew 2 adjust 3v66 and pci/f skew (3) rw 0 1 3v66-pci/f skew 1 adjust 3v66 and pci/f skew (3) rw 0 0 3v66-pci/f skew 0 adjust 3v66 and pci/f skew (3) rw 0 notes: 1. see agp/pci frequency selection table. 2. see smc table. 3. see 3v66 and pci/f skew table. byte 31: watchdog timer bit output(s) affected description/function 0 1 type power on 7 wd hard alarm timer 7 specify wd hard alarm time out waiting time. rw 0 6 wd hard alarm timer 6 time out time = wd hard alarm timer[7:0] * 290ms rw 0 5 wd hard alarm timer 5 default is 11*290 = 3.2s rw 0 4 wd hard alarm timer 4 rw 0 3 wd hard alarm timer 3 rw 1 2 wd hard alarm timer 2 rw 0 1 wd hard alarm timer 1 rw 1 0 wd hard alarm timer 0 rw 1
commercial temperature range IDTCV119E clock generator for desktop pc platforms 13 byte 32: wd soft reset timer wd soft alarm timer has to be shorter than wd hard alarm timer. wde and wd soft alarm bits, byte 33 bit 7 and bit 5, have to b e enabled for this soft alarm function. bit output(s) affected description/function 0 1 type power on 7 cpu wd hard alarm 0 = frequency select controlled by byte 25 bit 7 hw/i2c wdbs rw 0 safe frequency mode select 1 = cpu frequency specified wdcfs by wdbs[2:0] wdcfs[2:0] 6 wdcfs2 cpu wd time out safe frequency select (1) rw 0 5 wdcfs1 rw 0 4 wdcfs0 rw 0 3 wd soft alarm timer 3 specify wd soft alarm time out time rw 0 2 wd soft alarm timer 2 time out time = wd soft alarm timer[3:0]*290ms rw 0 1 wd soft alarm timer 1 default is 580ms. rw 1 0 wd soft alarm timer 0 rw 0 note: 1. see sw frequency selection table. byte 33: wd control bit output(s) affected description/function 0 1 type power on 7 wde watchdog enable disable enable rw 0 6 wd fs relatch relatch hw fs2, 1, 0 disable enable rw 0 in event of wd hard alarm time out 5 wd soft alarm enable wd soft alarm enable disable enable rw 0 4 agp/pci wd hard alarm in event of wd hard alarm time out hw/i2c wdafs rw 0 time out safe frequency mode select 0 = agp/pci frequency controlled by byte 30 bit 6 1 = agp/pci frequency specified by wdafs[2:0] 3 src smc 2 src ssc magnitude control (1) 1 2 src smc 1 src ssc magnitude control (1) 0 1 src smc 0 src ssc magnitude control (1) 1 0 reserve 0 byte 34 bit output(s) affected description/function 0 1 type power on 7 sw 24_48mhz control override 0 = controlled by hardware, 1 = controlled by bit 6 hw control controlled by rw 0 bit 6 6 24_48mhz select 48mhz 24mhz rw 0 5 reset#/pd# reset#/pd# mode select reset# pd# rw 0 4 0 3 0 2 1 0 note: 1. see smc table.
commercial temperature range 14 IDTCV119E clock generator for desktop pc platforms cpu and agp clock frequency selection band switch will take effect only when wd soft alarm time out is issued, which means there is a reset issued. even if the user changed bs[2:0], if there is no wd soft alarm, cpu pll still uses the old band. cpn[9:0] and apn[9:0] will be loaded into pll only when cpn0 and apn0 are written respectively. byte 32 bit 7, cpu wd hard alarm time out frequency select: byte 25 bit 7 00 latched hw fs[1:0] 01 bs[2:0], cfs[2:0], byte 25 10 wdbs[2:0], wdcfs[2:0], byte 26 and byte 32 11 wdbs[2:0], wdcfs[2:0], byte 26 and byte 32 wd soft and hard alarm/time out operation wd hard alarm timer [7:0] wd soft alarm timer [3:0] wde trigger watch dog circuit wd soft alarm time out if wd soft alarm enabled: set wdsrb issue reset# switch cpu pll band wd hard alarm time out set wdhrb issue reset# change cpu frequency (see byte 32, bit 7) change agp/pci frequency (see byte 33, bit 4) if wd fs relatch enabled, relatch hw fs2, fs1, fs0 reset byte 30 bit 7, and byte 25 bit 0, to 0 user only uses wd soft alarm when there is a band switch. it can be from hw to sw select, or in the sw select with band change . soft alarm timer has to be shorter than hard alarm timer. at the event of wd hard alarm time out, cpu safe return frequency is decided by two bits: byte 32 bit 7 and byte 25 bit 7. agp /pci safe return frequency is decided by byte 33 bit 4 and byte 30 bit 6. byte 30 bit 7, and byte 25 bit 0, will be reset to 0. byte 33 bit 4, agp/pci hard alarm time out frequency select: byte 30 bit 6 00 66/33mhz 01 afs[2:0], byte 28 10 wdafs, byte 28 11 wdafs, byte 28 cpu frequency byte 25 bit 0, bit 7 cpu frequency selected by: 00 hw fs[1:0] 01 bs[2:0], cfs[2:0], byte 25 10 cpn[9:0] * band resolution 11 cpn[9:0] * band resolution agp/pci frequency byte 30 bit 7, bit 6 agp/pci frequency selected by: 00 66/33 01 afs[2:0], byte 28 10 apn[9:0] * 0.223721591 11 apn[9:0] * 0.223721591
commercial temperature range IDTCV119E clock generator for desktop pc platforms 15 symbol parameter test conditions min. typ. max. unit v ih 3.3v input high voltage 3.3v 5% 2 ? v dd + 0.3 v v il 3.3v input low voltage 3.3v 5% v ss - 0.3 ? 0.8 v i ih input high current v in = v dd ?5 ? 5 a i il1 input low current v in = 0v, inputs with no pull-up resistors ?5 ? ? a i il2 input low current v in = 0v, inputs with pull-up resistors ?200 ? ? a i dd3.3op operating supply current full active, c l = full load ? ? 400 ma i dd3.3pd powerdown current all differential pairs driven ? ? 70 ma all differential pairs tri-stated ? ? 12 f i input frequency (2) v dd = 3.3v ? 14.31818 ? mhz l pin pin inductance (3) ?? 7 nh c in logic inputs ? ? 5 c out input capacitance (3) output pin capacitance ? ? 6 pf c inx x1 and x2 pins ? ? 5 t stab clock stabilization (3,4) from v dd power-up or de-assertion of pd# to first clock ? ? 1.8 ms modulation frequency (3) triangular modulation 30 ? 33 khz t drive _src (3) src output enable after pci_stop# de-assertion ? ? 15 ns t drive _pd# (3) cpu output enable after pd# de-assertion ? ? 300 us t fall _pd# (3) fall time of pd# ? ? 5 ns t rise _pd# (4) rise time of pd# ? ? 5 ns t drive _cpu_stop# (3) cpu output enable after cpu_stop# de-assertion ? ? 10 us t fall _cpu_stop# (3) fall time of pd# ? ? 5 ns t rise _cpu_stop# (4) rise time of pd# ? ? 5 ns electrical characteristics - input / supply / common output parameters following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5% notes: 1. available to cv104, cv105, cv107, and cv109. 2. input frequency should be measured at the ref output pin and tuned to ideal 14.31818mhz to meet ppm frequency accuracy on pll outputs. 3. this parameter is guaranteed by design, but not 100% production tested. 4. see timing diagrams for timing requirements.
commercial temperature range 16 IDTCV119E clock generator for desktop pc platforms symbol parameter test conditions min. typ. max. unit z o current source output impedance (2) v o = v x 3000 ? ? ? v ovs maximum voltage (overshoot) ? ? v h + 0.3 v v uds minimum voltage (undershoot) -0.3 ? ? v v high voltage high (2) statistical measurement on single-ended signal using 660 ? 850 mv v low voltage low (2) oscilloscope math function ?150 ? 150 v ovs max voltage (2) measurement on single-ended signal using absolute value ? ? 1150 mv v uds min voltage (2) ?300 ? ? v cross(abs) crossing voltage (abs) (2) 250 ? 550 mv d - v cross crossing voltage (var) (2) variation of crossing over all edges ? ? 140 mv ppm long accuracy (2,3) see t period min. - max. values ?300 ? 300 ppm 400mhz nominal, no intel spec 2.4993 ? 2.5008 333.33mhz nominal, no intel spec 2.9991 ? 3.0009 266.66mhz nominal, no intel spec 3.7489 ? 3.7511 t period average period (3) 200mhz nominal 4.9985 ? 5.0015 ns 166.66mhz nominal 5.9982 ? 6.0018 133.33mhz nominal 7.4978 ? 7.5023 100mhz nominal 9.997 ? 10.003 400mhz spread, no intel spec 2.4993 ? 2.5008 333.33mhz spread, no intel spec 2.9991 ? 3.0009 266.66mhz spread, no intel spec 3.7489 ? 3.7511 t period average period (3) 200mhz spread 4.9985 ? 5.0266 ns 166.66mhz spread 5.9982 ? 6.032 133.33mhz spread 7.4978 ? 7.54 100mhz spread 9.997 ? 10.0533 t r rise time (2) v ol = 0.175v, v oh = 0.525v 175 ? 700 ps t f fall time (2) v ol = 0.175v, v oh = 0.525v 175 ? 700 ps d-t r rise time variation (2) ? ? 125 ps d-t f fall time variation (2) ? ? 125 ps d t3 duty cycle (2) measurement from differential waveform 45 ? 55 % t sk 3 skew (2) v t = 50% ? ? 100 ps t jcyc - cyc jitter, cycle to cycle (2) measurement from differential waveform ? ? 85 ps electrical characteristics - cpu and src 0.7 current mode differential pair (1) following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%; c l = 2pf notes: 1. src clock outputs run only at 100mhz or 200mhz. specs for 133.33 and 166.66 do not apply to src clock pair. 2. this parameter is guaranteed by design, but not 100% production tested. 3. all long term accuracy and clock period specifications are guaranteed with the assumption that the ref output is at 14.31818m hz.
commercial temperature range IDTCV119E clock generator for desktop pc platforms 17 symbol parameter test conditions min. typ. max. unit ppm long accuracy (1,2) see tperiod min. - max. values -300 ? 300 ppm v oh output high voltage i oh = -1ma 2.4 ? ? v v ol output low voltage i ol = 1ma ? ? 0.55 v t period clock period (2) 66mhz output nominal 14.9955 ? 15.0045 ns 66mhz output spread 14.9955 ? 15.0799 i oh output high current v oh at min. = 1v -33 ? ? ma v oh at max. = 3.135v ? ? -33 i ol output low current v ol at min. = 1.95v 30 ? ? ma v ol at max. = 0.4v ? ? 38 edge rate (1) rising/falling edge rate 1 ? 4 v/ns t r1 rise time (1) v ol = 0.4v, v oh = 2.4v 0.5 ? 2 ns t f1 fall time (1) v ol = 0.4v, v oh = 2.4v 0.5 ? 2 ns t sk1 skew (1) v t = 1.5v ? ? 250 ps d t1 duty cycle (1) v t = 1.5v 45 ? 55 % t jcyc - cyc jitter (1) v t = 1.5v, 3v66 ? ? 250 ps electrical characteristics - 3v66 following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%; c l = 10 - 30pf notes: 1. this parameter is guaranteed by design, but not 100% production tested. 2. all long term accuracy and clock period specifications are guaranteed with the assumption that the ref output is at 14.31818m hz. symbol parameter test conditions min. typ. max. unit ppm long accuracy (1,2) see tperiod min. - max. values ? ? 300 ppm t period clock period (2) 33.33mhz output nominal 29.991 ? 30.009 ns 33.33mhz output spread 29.991 ? 30.1598 v oh output high voltage i oh = -1ma 2.4 ? ? v v ol output low voltage i ol = 1ma ? ? 0.55 v i oh output high current v oh at min. = 1v -33 ? ? ma v oh at max. = 3.135v ? ? -33 i ol output low current v ol at min. = 1.95v 30 ? ? ma v ol at max. = 0.4v ? ? 38 edge rate (1) rising edge rate 1 ? 4 v/ns edge rate (1) falling edge rate 1 ? 4 v/ns t r1 rise time (1) v ol = 0.4v, v oh = 2.4v 0.5 ? 2 ns t f1 fall time (1) v ol = 0.4v, v oh = 2.4v 0.5 ? 2 ns d t1 duty cycle (1) v t = 1.5v 45 ? 55 % t sk1 skew (1) v t = 1.5v ? ? 500 ps t jcyc - cyc jitter (1) v t = 1.5v ? ? 250 ps electrical characteristics - pciclk / pciclk_f following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%; c l = 10 - 30pf notes: 1. this parameter is guaranteed by design, but not 100% production tested. 2. all long term accuracy and clock period specifications are guaranteed with the assumption that the ref output is at 14.31818m hz.
commercial temperature range 18 IDTCV119E clock generator for desktop pc platforms notes: 1. this parameter is guaranteed by design, but not 100% production tested. 2. all long term accuracy and clock period specifications are guaranteed with the assumption that the ref output is at 14.31818m hz. symbol parameter test conditions min. typ. max. unit ppm long accuracy (1,2) see tperiod min. - max. values ? ? 300 ppm t period clock period (2) 48mhz output nominal 20.8271 ? 20.8396 ns v oh output high voltage i oh = -1ma 2.4 ? ? v v ol output low voltage i ol = 1ma ? ? 0.55 v i oh output high current v oh at min. = 1v -33 ? ? ma v oh at max. = 3.135v ? ? -33 i ol output low current v ol at min. = 1.95v 30 ? ? ma v ol at max. = 0.4v ? ? 38 edge rate (1) rising edge rate 1 ? 2 v/ns edge rate (1) falling edge rate 1 ? 2 v/ns t r1 rise time (1) v ol = 0.4v, v oh = 2.4v 1 ? 2 ns t f1 fall time (1) v ol = 0.4v, v oh = 2.4v 1 ? 2 ns d t1 duty cycle (1) v t = 1.5v 45 ? 55 % t jcyc - cyc jitter (1) ? ? 350 ps electrical characteristics, 48mhz, usb and v ch following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%; c l = 10 - 20pf symbol parameter test conditions min. typ. max. unit ppm long accuracy (1,2) see tperiod min. - max. values ? ? 300 ppm t period clock period (2) 48mhz output nominal 20.8271 ? 20.8396 ns v oh output high voltage i oh = -1ma 2.4 ? ? v v ol output low voltage i ol = 1ma ? ? 0.55 v i oh output high current v oh at min. = 1v -33 ? ? ma v oh at max. = 3.135v ? ? -33 i ol output low current v ol at min. = 1.95v 30 ? ? ma v ol at max. = 0.4v ? ? 38 edge rate (1) rising edge rate 2 ? 4 v/ns edge rate (1) falling edge rate 2 ? 4 v/ns t r1 rise time (1) v ol = 0.4v, v oh = 2.4v 0.5 ? 1 ns t f1 fall time (1) v ol = 0.4v, v oh = 2.4v 0.5 ? 1 ns d t1 duty cycle (1) v t = 1.5v 45 ? 55 % t jcyc - cyc jitter (1) ? ? 350 ps electrical characteristics, dot 48mhz following conditions apply unless otherwise specified: operating condition: t a = 0c to +70c, supply voltage: v dd = 3.3v 5%; c l = 10 - 20pf notes: 1. this parameter is guaranteed by design, but not 100% production tested. 2. all long term accuracy and clock period specifications are guaranteed with the assumption that the ref output is at 14.31818m hz.
commercial temperature range IDTCV119E clock generator for desktop pc platforms 19 pd#, power down pd# is an asynchronous active low input used to shut off all clocks cleanly prior to clock power. when pd# is asserted low all clocks will be driven low before turning off the vco. in pd# de-assertion all clocks will start without glitches. pd# assertion pd# should be sampled low by two consecutive cpu# rising edges before stopping clocks. all single-ended clocks will be held low on their next high to low transition. all differential clocks will be held high on the next high to low transition of the complimentary clock. if th e control register determining to drive mode is set to ?tri-state?, the differential pair will be stopped in tri-state mode, undriven. when the drive mode but corresp onding to the cpu or src clock of interest is set to ?0? the true clock will be driven high at 2 x i ref and the complementary clock will be tristated. if the control register is programmed to ?1? both clocks will be tristated. p wrdwn # cpu 133mhz cpu# 133mhz src 100mhz src# 100mhz usb 48mhz pci 33mhz ref 14.31818 p wrdwn # cpu cpu# src src# pcif/pci usb 3v66 ref 1 normal normal normal normal 33mhz 48mhz 66mhz 14.318mhz 0i ref * 2 or float float i ref * 2 or float float low low low low
commercial temperature range 20 IDTCV119E clock generator for desktop pc platforms pd# de-assertion the time from the de-assertion of pd# or until power supply ramps to get stable clocks will be less than 1.8ms. if the drive mo de control bit for pd# tristate is programmed to ?1? the stopped differential pair must first be driven high to a minimum of 200mv in less than 300s of pd# de assertion. p wrdwn # cpu 133mhz cpu# 133mhz src 100mhz src# 100mhz usb 48mhz pci 33mhz ref 14.31818 t stable <1.8ms t drive_pwrdwn# <300 s, <200mv n programming jitter measurement tested on idt test board, 10" trace, 10pf loading. measured at cpu0, differential active probe. data showed may vary due to cmos process. 100mhz mode n = output freq. (mhz) cpu jitter (ps) 200h (512) 115 80 300h (768) 172 51 3ffh (1023) 229 65 166mhz mode n = output freq. (mhz) cpu jitter (ps) 200h (512) 204 71 300h (768) 305 72 3ffh (1023) 407 92 133mhz mode n = output freq. (mhz) cpu jitter (ps) 200h (512) 153 76 300h (768) 229 79 3ffh (1023) 306 72 200mhz mode n = output freq. (mhz) cpu jitter (ps) 200h (512) 229 68 300h (768) 344 84 3ffh (1023) 458 82
commercial temperature range IDTCV119E clock generator for desktop pc platforms 21 ordering information xxx xx package pv small shrink outline package clock generator for desktop pc platforms 119e device type x grade blank idtcv commercial temperature range (0c to +70c) corporate headquarters for sales: for tech support: 2975 stender way 800-345-7015 or 408-727-6116 logichelp@idt.com santa clara, ca 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com

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